1. Field of the Invention
The present invention relates to driving a panel, such as a Plasma Display Panel (PDP), and more particularly, to a panel driving method with an improved reset period and a program storage device, readable by a machine, tangibly embodying a program of instructions executable by the machine to perform the panel driving method with an improved reset period.
2. Description of the Related Art
In a single cell of a PDP, address electrode lines A1, A2, . . . Am, dielectric layers, Y-electrode lines Y1, . . . , Yn, X-electrode lines X1, . . . , Xn, phosphor layers, barrier walls, and a protective layer, for example, a magnesium oxide (MgO) layer, are provided between a front glass substrate and a rear glass substrate of the surface discharge PDP.
The address electrode lines A1 through Am are formed on the front surface of the rear glass substrate in a predetermined pattern. A rear dielectric layer is formed on the surface of the rear glass substrate having the address electrode lines A1 through Am. The barrier walls are formed on the front surface of the rear dielectric layer parallel to the address electrode lines A1 through Am. The barrier walls partition discharge regions of respective display cell and serve to prevent cross talk between display cells. The phosphor layers are formed between the barrier walls.
The X-electrode lines X1 through Xn and the Y-electrode lines Y1 through Yn are formed on the rear surface of the front glass substrate in a predetermined pattern to be orthogonal to the address electrode lines A1 through Am. The respective intersections define display cells. Each of the X-electrode lines X1 through Xn can include a transparent electrode line Xna formed of a transparent conductive material, e.g., Indium Tin Oxide (ITO), and a metal electrode line Xnb for increasing conductivity. Each of the Y-electrode lines Y1, Y2, . . . , Yn can include a transparent electrode line Yna formed of a transparent conductive material, e.g., ITO, and a metal electrode line Ynb for increasing conductivity. A front dielectric layer is deposited on the entire rear surface of the front glass substrate having the rear surfaces of the X-electrode lines X1, X2, . . . , Xn and the Y-electrode lines Y1, Y2, . . . , Yn. The protective layer, e.g., a MgO layer, for protecting the panel against a strong electrical field, is deposited on the entire rear surface of the front dielectric layer. A gas for forming a plasma is hermetically sealed in a discharge space.
In driving such PDP, usually, reset step, address step, and sustain step are sequentially performed in each subfield. In reset step, charges are uniformized in display cells to be driven. In address step, a charge state of display cells to be selected and a charge state of display cells to be unselected are set up. In sustain step, a display discharge occurs in the selected display cells. A plasma is produced from the plasma forming gas in the display cells where the display discharge occurs. The plasma emits ultraviolet rays exciting the phosphor layers in the display cells, so that light is emitted.
An address-display separation driving method for the PDP having such a structure is discussed in U.S. Pat. No. 5,541,618.
A driving apparatus for the PDP discussed above includes an image processor, a logic controller, an address driver, an X-driver, and a Y-driver. The image processor converts an I l external analog image signal into a digital signal to generate an internal image signal, for example, 8-bit red (R) video data, 8-bit green (G) video data, and 8-bit blue (B) video data, a clock signal, a vertical synchronizing signal, and a horizontal synchronizing signals. The logic controller generates drive control signals Sa, Sy, and Sx in response to the internal image signals from the image processor. The address driving unit processes the address signal SA among the drive control signals SA, SY, and SX output from the logic controller to generate a display data signal and applies the display data signal to address electrode lines. The X-driver processes the X-drive control signal SX among the drive control signals SA, SY, and SX output from the logic controller and applies the result of processing to X-electrode lines. The Y-driver processes the Y-drive control signal SY among the drive control signals SA, SY, and SX output from the logic controller 302 and applies the result of processing to Y-electrode lines.
With respect to Y-electrode lines of the PDP discussed above, to realize a time-division grayscale display, a unit frame can be divided into a predetermined number of subfields, e.g., 8 subfields SF1, SF2, . . . , SF8. In addition, the individual subfields SF1 through SF8 are composed of reset periods (not shown), respectively, address periods A1, A2, . . . , A8, and sustain periods S1, S2, . . . , S8, respectively.
During each of the address periods A1 through A8, display data signals are supplied to address electrode lines A1 through Am and simultaneously, a scan pulse is sequentially supplied to the Y-electrode lines Y1 through Yn.
During each of the sustain periods S1 through S8, a pulse for display discharge is alternately supplied to the Y-electrode lines Y1 through Yn and the X-electrode lines X1 through Xn, thereby provoking display discharge in discharge cells in which wall charges are induced during each of the address periods A1 through A8.
The luminance of the PDP is proportional to a total length of the sustain periods S1 through S8 in a unit frame. When a unit frame forming a single image is expressed by 8 subfields and 256 grayscales, different numbers of sustain pulses can be allocated to the respective subfields at a ratio of 1:2:4:8:16:32:64:128. Luminance corresponding to 133 grayscales can be obtained by addressing cells and sustaining a discharge during a first subfield SF1, a third subfield SF3, and an eighth subfield SF8.
A sustain period allocated to each subfield can be variably determined depending upon weights, which are supplied to the respective subfields according to an Automatic Power Control (APC) level, and can be variously changed taking account of gamma characteristics or panel characteristics. For example, a grayscale level allocated to a fourth subfield SF4 can be lowered from 8 to 6, while a grayscale level allocated to a sixth subfield SF6 can be increased from 32 to 34. In addition, the number of subfields constituting a single frame can be variously changed according to design specifications.
A single subfield SF of an Alternating Current (AC) PDP includes a reset period PR, an address period PA, and a sustain period PS.
During the reset period PR, a reset pulse is supplied to all of the scan electrodes Y1 through Yn, thereby initializing a state of wall charges in each cell. The reset period PR is performed before entering the address period PA. The reset period PR is provided prior to the address period PA. Since the initialization is performed throughout the PDP1 during the reset period PR, highly uniform and desirable distribution of wall charges can be obtained. The cells initialized during the reset period PR have similar wall charge conditions to one another. The reset period PR is followed by the address period PA. During the address period PA, a bias voltage Ve is supplied to the common electrodes X, and the scan electrodes Y1 through Yn and the address electrodes A1 through Am corresponding to cells to be displayed are simultaneously turned on to select the cells. After the address period PA, a sustain pulse Vs is alternately supplied to the common electrodes X and the scan electrodes Y1 through Yn during the sustain period PS. During the sustain period PS, a voltage VG of a low level is supplied to the address electrodes A1 through Am.
During the reset period PR, a ramp rising period of the scan electrodes Y1 through Yn is provided to minimize the length of visible rays emitted during a write discharge and facilitate initialization of cells.
In the PDP driving method discussed above, a single subfield SF includes a reset period PR, an address period PA, and a sustain period PS. However, there is also another panel driving method in which only some of a plurality of subfields constituting one TV field include a reset period PR to minimize visible rays during the write discharge. In this method, the single TV field includes at least one reset period PR and a plurality of subfields. A single subfield includes an address period PA and a sustain period PS. Also, a reset period PR having a constant time is supplied irrespective of the weight of the sustain period PS in a single TV field.